Dr. Giles Humpston

Cambridge Nanotherm, Applications Manager

Dr. Giles Humpston

Cambridge Nanotherm, Applications Manager

Biography

Dr. Humpston is a metallurgist by profession and has a doctorate in alloy phase equilibria.  He is a cited inventor on more than 250 patents and has co-authored over 150 papers as well as several text books.  Dr Humpston currently works as the Applications Manager for Cambridge Nanotherm on thermal substrate technologies.


Thermal Management for Chip-Scale Packaged Lighting Modules

A new innovation in LED technology is the development of chip scale packaging (CSP) for general lighting applications. Chip scale packages are defined as being not more than 20% larger than the die itself and save on materials and assembly processes (such as eliminating the expensive ceramic submount) helping to drive down manufacturing costs. Despite the relatively recent release of high-power CSP LEDs, industry analysts estimate CSPs will make up 34% of the high-power LED market by 2020.

Tightly packed arrays of CSP LEDs are the ideal candidate to replace chip-on-board (COB) devices, with the considerable advantage that they can be readily manufactured using standard pick-and place infrastructure without the complications of handling bare die and applying phosphors. This enables light engine designers to conceive and cost effectively manufacture LED modules using standard PCB assembly equipment rather than the specialist equipment required for placing bare die.

The design of CSPs can also reduce optical cross-talk (particularly with CSPs that only emit light from the top surface), enabling CSP LEDs to be packed in dense arrays to produce ‘device-on-board’ light engines. This is hugely beneficial to module and light engine designers who can create smaller, brighter and cheaper devices.
However, there is a catch. CSP LEDs are designed to be soldered directly onto a metal clad PCB (MCPCB).  But the combination of small size, high power and dense array packing produces intense thermal flux that many conventional MCPCBs fail to manage owing to inadequate z-axis thermal conductivity through the dielectric.  The conventional workaround of increasing the thickness of the copper layer on the MCPCB provides only marginal benefit especially as the upper limit is constrained by the need to achieve narrow gaps (typically <200um) in the wiring trace to suit the tiny lands on CSP LEDs.  This paper will present computer simulations supported by actual temperature measurements to demonstrate that CSP LEDs must be used with MCPCBs having exceptionally high axial thermal conductivity in order to keep junction temperatures within safe limits and achieve uniform temperature across CSP arrays.

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